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74AC374, 74ACT374 -- Octal D-Type Flip-Flop with 3-STATE Outputs
January 2008
74AC374, 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs
Features
ICC and IOZ reduced by 50% Buffered positive edge-triggered clock 3-STATE outputs for bus-oriented applications Outputs source/sink 24mA See 273 for reset version See 377 for clock enable version See 373 for transparent latch version See 574 for broadside pinout version See 564 for broadside pinout version with inverted
General Description
The AC/ACT374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops.
outputs
ACT374 has TTL-compatible inputs
Ordering Information
Order Number
74AC374SC 74AC374SJ 74AC374MTC 74AC374PC 74ACT374SC 74ACT374SJ 74ACT374MSA 74ACT374MTC 74ACT374PC
Package Number
M20B M20D MTC20 N20A M20B M20D MSA20 MTC20 N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard.
(c)1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com
74AC374, 74ACT374 -- Octal D-Type Flip-Flop with 3-STATE Outputs
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Description
Pin Names
D0-D7 CP OE O0-O7
Description
Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs
Functional Description
The AC/ACT374 consists of eight edge-triggered flipflops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.
Truth Table
Inputs Dn
H L X X H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition
Outputs OE
L L H
CP
On
H L Z
(c)1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5.0
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74AC374, 74ACT374 -- Octal D-Type Flip-Flop with 3-STATE Outputs
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
(c)1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com 3
74AC374, 74ACT374 -- Octal D-Type Flip-Flop with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VCC IIK Supply Voltage DC Input Diode Current VI = -0.5V VI = VCC + 0.5 VI IOK DC Input Voltage DC Output Diode Current VO = -0.5V VO = VCC + 0.5V VO IO DC Output Voltage
Parameter
Rating
-0.5V to +7.0V -20mA +20mA -0.5V to VCC + 0.5V -20mA +20mA -0.5V to VCC + 0.5V 50mA 50mA -65C to +150C 140C
DC Output Source or Sink Current
ICC or IGND DC VCC or Ground Current per Output Pin TSTG Storage Temperature TJ Junction Temperature
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC Supply Voltage AC ACT VI VO TA V / t V / t Input Voltage Output Voltage Operating Temperature
Parameter
Rating
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC -40C to +85C 125mV/ns 125mV/ns
Minimum Input Edge Rate, AC Devices: VIN from 30% to 70% of VCC, VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices: VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V
(c)1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com 4
74AC374, 74ACT374 -- Octal D-Type Flip-Flop with 3-STATE Outputs
DC Electrical Characteristics for AC
TA = +25C Symbol
VIH
TA = -40C to +85C Units
V 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 1.0 2.5 A A V V V
Parameter
Minimum HIGH Level Input Voltage
VCC (V)
3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5
Conditions
VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50A
Typ.
1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1
Guaranteed Limits
3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86
VIL
Maximum LOW Level Input Voltage
VOH
Minimum HIGH Level Output Voltage
VIN = VIL or VIH, IOH = -12mA VIN = VIL or VIH, IOH = -24mA VIN = VIL or VIH, IOH = -24mA(1) 0.002 0.001 0.001 VIN = VIL or VIH, IOL = 12mA VIN = VIL or VIH, IOL = 24mA VIN = VIL or VIH, IOL = 24mA(1) VI = VCC, GND VI (OE) = VIL, VIH; VI = VCC, GND; VO = VCC, GND VOLD = 1.65V Max. VOHD = 3.85V Min. VIN = VCC or GND IOUT = 50A
VOL
Maximum LOW Level Output Voltage
3.0 4.5 5.5 3.0 4.5 5.5
0.1 0.1 0.1 0.36 0.36 0.36 0.1 0.25
IIN(2) IOZ
Maximum Input Leakage Current Maximum 3-STATE Leakage Current Minimum Dynamic Output Current(3) Maximum Quiescent Supply Current
5.5 5.5
IOLD IOHD ICC
(2)
5.5 5.5 5.5
75 -75 4.0 40.0
mA mA A
Notes: 1. All outputs loaded; thresholds on input associated with output under test. 2. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. 3. Maximum test duration 2.0ms, one output loaded at a time.
(c)1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5.0
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74AC374, 74ACT374 -- Octal D-Type Flip-Flop with 3-STATE Outputs
DC Electrical Characteristics for ACT
TA = +25C Symbol
VIH VIL VOH
TA = -40C to +85C Units
V V V 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 2.5 1.5 75 -75 A A mA mA mA A V
Parameter
Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage
VCC (V)
4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5
Conditions
VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50A VIN = VIL or VIH, IOH = -24mA VIN = VIL or VIH, IOH = -24mA(4) IOUT = 50A VIN = VIL or VIH, IOL = 24mA VIN = VIL or VIH, IOL = 24mA(4) VI = VCC, GND VI = VIL, VIH; VO = VCC, GND VI = VCC - 2.1V VOLD = 1.65V Max. VOHD = 3.85V Min. VIN = VCC or GND
Typ.
1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4
Guaranteed Limits
3.86 4.86 0.001 0.001 0.1 0.1 0.36 0.36 0.1 0.25 0.6
VOL
Maximum LOW Level Output Voltage
4.5 5.5 4.5 5.5
IIN IOZ ICCT IOLD IOHD ICC
Maximum Input Leakage Current Maximum 3-STATE Leakage Current Maximum ICC/Input Minimum Dynamic Output Current(5) Maximum Quiescent Supply Current
5.5 5.5 5.5 5.5 5.5 5.5
4.0
40.0
Notes: 4. All outputs loaded; thresholds on input associated with output under test. 5. Maximum test duration 2.0ms, one output loaded at a time.
(c)1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com 6
74AC374, 74ACT374 -- Octal D-Type Flip-Flop with 3-STATE Outputs
AC Electrical Characteristics for AC
TA = +25C, CL = 50pF Symbol
fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ
TA = -40C to +85, CL = 50pF Min.
60 100 13.5 9.5 12.5 9.0 11.5 8.5 11.5 8.5 12.5 11.0 11.5 8.5 1.5 1.5 2.0 1.5 1.5 1.0 1.5 1.0 2.0 2.0 1.0 1.0 15.5 10.5 14.0 10.0 13.0 9.5 13.0 9.5 14.5 12.5 12.5 10.0 ns ns ns ns ns ns
Parameter
Maximum Clock Frequency Propagation Delay, CP to On Propagation Delay, CP to On Output Enable Time Output Enable Time Output Disable Time Output Disable Time
VCC (V)(6)
3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Min.
60 100 3.0 2.5 2.5 2.0 3.0 2.0 2.5 2.0 3.0 2.0 2.0 1.5
Typ.
110 155 11.0 8.0 10.0 7.0 9.5 7.0 9.0 6.5 10.5 8.0 8.0 6.5
Max.
Max.
Units
MHz
Note: 6. Voltage range 3.3 is 3.3V 0.3V. Voltage range 5.0 is 5.0V 0.5V.
AC Operating Requirements for AC
TA = +25C, CL = 50pF Symbol
tS tH tW
TA = -40C to +85C, CL = 50pF Units
ns ns ns 6.0 4.5 1.0 1.5 6.0 4.5
Parameter
Setup Time, HIGH or LOW, Dn to CP Hold Time, HIGH or LOW, Dn to CP CP Pulse Width, HIGH or LOW
VCC (V)(7)
3.3 5.0 3.3 5.0 3.3 5.0
Typ.
2.0 1.0 -1.0 0 4.0 2.5
Guaranteed Minimum
5.5 4.0 1.0 1.5 5.5 4.0
Note: 7. Voltage range 3.3 is 3.3V 0.3V. Voltage range 5.0 is 5.0V 0.5V.
(c)1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com 7
74AC374, 74ACT374 -- Octal D-Type Flip-Flop with 3-STATE Outputs
AC Electrical Characteristics for ACT
TA = +25C, CL = 50pF Symbol
fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ
TA = -40C to +85C, CL = 50pF Min.
90
Parameter
Maximum Clock Frequency Propagation Delay, CP to On Propagation Delay, CP to On Output Enable Time Output Enable Time Output Disable Time Output Disable Time
VCC (V)(8)
5.0 5.0 5.0 5.0 5.0 5.0 5.0
Min.
100 2.0 2.0 2.0 1.5 1.5 1.5
Typ.
160 8.5 8.0 8.0 8.0 8.5 7.0
Max.
Max.
Units
MHz
10.0 9.5 9.5 9.0 11.5 8.5
2.0 1.5 1.5 1.5 1.0 1.0
11.5 11.0 10.5 10.5 12.5 10.0
ns ns ns ns ns ns
Note: 8. Voltage range 5.0 is 5.0V 0.5V.
AC Operating Requirements for ACT
TA = +25C, CL = 50pF Symbol
tS tH tW
TA = -40C to +85C, CL = 50pF Units
ns ns ns 5.5 1.5 5.0
Parameter
Setup Time, HIGH or LOW, Dn to CP Hold Time, HIGH or LOW, Dn to CP CP Pulse Width, HIGH or LOW
VCC (V)(9)
5.0 5.0 5.0
Typ.
1.0 0 2.5
Guaranteed Minimum
5.5 1.5 5.0
Note: 9. Voltage range 5.0 is 5.0V 0.5V.
Capacitance
Symbol
CIN
Parameter
Input Capacitance
Conditions
VCC = OPEN
Typ.
4.5
Units
pF
(c)1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com 8
74AC374, 74ACT374 -- Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions
13.00 12.60 11.43
20 B 11 A
9.50 10.65 7.60 10.00 7.40 2.25
1 PIN ONE INDICATOR
0.51 0.35
0.25
M
10
1.27
CBA
1.27
0.65
LAND PATTERN RECOMMENDATION
2.65 MAX
SEE DETAIL A
C
0.33 0.20
0.10 C SEATING PLANE
0.75 0.25 (R0.10) (R0.10)
8 0
X 45
0.30 0.10
NOTES: UNLESS OTHERWISE SPECIFIED
GAGE PLANE
0.25 1.27 0.40 (1.40)
A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) CONFORMS TO ASME Y14.5M-1994 E) LANDPATTERN STANDARD: SOIC127P1030X265-20L F) DRAWING FILENAME: MKT-M20BREV3
SEATING PLANE
DETAIL A
SCALE: 2:1
Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c)1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com 9
74AC374, 74ACT374 -- Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions (Continued)
Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c)1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com 10
74AC374, 74ACT374 -- Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions (Continued)
Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c)1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com 11
74AC374, 74ACT374 -- Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions (Continued)
26.92 24.89
PIN #1
7.11 6.09
(0.97)
1.78 1.14
7 TYP
3.43 3.17 5.33 MAX
7 TYP
7.87
2.54 0.36 0.56
.001[.025] C
3.55 3.17 0.38 MIN
7.62 10.92 MAX 0.20 0.35
NOTES:
Figure 4. 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c)1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com 12
74AC374, 74ACT374 -- Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions (Continued)
Figure 5. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c)1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5.0
www.fairchildsemi.com 13
74AC374, 74ACT374 -- Octal D-Type Flip-Flop with 3-STATE Outputs
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Rev. I32
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Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
(c)1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Rev. 1.5.0
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